Ask HN: What does RISC-V custom chips for under $100K mean?
In 2016, SiFive blogged about custom chips for under $100K[1]. What does this mean in practice for a business? What does a business get if they give SiFive $100K? Does the business have to give SiFive anything in addition to $100K such as a schematic? What are the steps between giving SiFive $100K and getting physical chips in your hands?
> At the workshop, people asked me what it would cost to make a chip with SiFive. The room went quiet … people expected me to dance around the topic (like all other people do). Jaws dropped when I simply said “system architects and designers can get customized chips for less than $100,000” – less than the cost of just licensing most CPUs today.
[1] https://www.sifive.com/blog/custom-chips-for-under-100k
In 2016 that would be a E31 core, user-specified amount of data SRAM and icache (also SRAM), XIP from external SPI flash, user-specified number of GPIOs. Possibly integrating some simple customer peripheral IP as a memory-mapped device, or MAYBE with a simple custom instruction as a functional unit, SiFive doing a little NRE on that, and doing a $30k 180nm shuttle run giving ~300 chips.
If you could give SiFive your desired peripheral or custom instruction already integrated with Rocket and working on an FPGA (Arty) then you'd get it for under $100k for sure -- if you made SiFive do the work it would rapidly get to be more.
Disclaimer: I was an early customer for the HiFive1 (December 2016) and then worked at SiFive from early 2018 to early 2020, but I don't speak for them.
Thanks for replying! This is one of those moments when one is reminded how amazing HN can be.
So, for example, if a business sends SiFive $100K and a copy of OpenRISC, they would receive ~300 chips that could then be used in a commercial product?
If a business then wants to order another 300 chips (or more), would they only need to pay SiFive the $30K? Does the $30K price fluctuate? Does E31 core have an end of life? In the event that EOL is reached, or SiFive ceases to exist, can the business make these chips somewhere else or are they screwed?
Quick note - I’ve been where you are on hardware, which I imagine is “interested and curious and might have a use case”. Silicon is an industry that is related to software, but in no way the same, and it’s a fairly complex stack, with its own unique supply chains and considerations.
All that said, if you’re exploring, have fun! If you’re getting serious I’d recommend you find someone who can help you navigate it; there are many surprising things to learn as you go.
For instance, to answer your question on chips: all chips are made by ‘taping out’ - a process that yields the masks that can be used to make chips. These are only good with a specific chip maker, and will live with that chip maker near the hardware that is used to make the chips forever. It’s expensive to design the chip, and expensive to tape out, but once you have something it’s relatively cheap to make more of them.
180nm is potato quality - many many generations behind. So far behind it might actually be more expensive to get chips than at 110/65nm, although I’m only speculating here.
A shuttle run means the vendor is going to put your chip designs onto a wafer with a bunch of other ones at the same time; it’s a way to share out the costs for a tape out with other customers. The general idea of a 180nm tape out is likely that you want some parts to test in your infrastructure / build ahead of your full launch. Think of it like a compile with -debug turned all the way up.
Usually you’d then either adjust the design and re-do a shuttle run (your compile turned up real problems or your use case changed), or you’d shrink and make your own wafer, (turn on optimization and compile for deployment). Shrinking from 180 to 110 or 65 is likely almost totally an automatic process these days; as you go smaller, analog physics makes this challenging.
So, upshot: you probably could ask for another shuttle run, but you’d have a higher part cost than your first run because you’d be paying for the whole wafer alone this time, but only able to use the part that has your chips on it.
And, you’d need to be in a world where you really wanted another 300 chips of the same potato speed (and possibly quality) as your first run. Most likely a silicon consultant would find a more efficient use case for your needs, whether that’s a small geometry FPGA that is programmable, an existing chip (there are A LOT of chips in the world), or some other solution.
Anyway, have fun if you get into it — fascinating world.
Can confirm that lots of our ~10 year old designs are getting a re-spin on newer processes for exactly this reason. The availability of the old ones is going down.
As for "can you order more if SiFive goes out of business": the detail here is going to be in all the other bits on the chip. Maybe they're free licensed, maybe they're not. You probably wouldn't get the GDSII that SiFive sent to the fab. You'd need to arrange another shuttle run. You might be too small for the fab to return your calls.
It's a pretty niche kind of manufacturing activity. Not many businesses really need a custom CPU.
What is would you consider the rule of thumb/guideline/standard/considerations for a business needing a custom CPU?
Like what would drive the cost of a custom chip being cheaper than adapting something more of the shelf?
> You might be too small for the fab to return your calls.
How long till there is a self-service SaaS for this?
It's necessarily an interactive process. They will want an NDA (you generally can't get the fab "library" or even process information without this!). They'll want to do sales work on you. There's enough bits where they will want to check your work and understanding because it reflects badly on _them_ if the result doesn't work in a way which could be deemed their fault. A lot of this stuff already exists for PCB manufacturers and has very gradually been automated into a SaaS, but chip shuttle is a much smaller market than PCBs and will remain that way.
An example list of steps: https://www.usjpc.com/en/ourbusiness/shuttle.php
https://tinytapeout.com/ <-- there is this project ...
About as soon as a SaaS self-service to order a piloted jet plane.
Either you're really big and can put serious resources into R&D and production, or you can have a few toy-sized offerings for the lowest end that are only good for highly custom or testing purposes, or you are too small to care.
a couple reasons why this is unlikely anytime soon. one is that the engineering processes between the designer and the fab are still too tightly coupled. some for good reason and some that they want to sell you engineering servives.
the other is that the fab schedule is heavily laced with sales politics. getting a timely slot is largely a factor of how important a customer you are and none about scheduling work. they have as much work as they could ever want.
So, if I am hearing you correctly, someone starting this up would have all the customers they could ever want simply by being easy to use, well documented, and no sales bullshit?
I am not an EE nor do I design chips but I think that the quality of your fab process and the usefulness of your blocks library would be more important success factors in acquiring customers than those you listed.
EE chip designer here. this is 100% correct. just one point to add: quality of fab process as is also doesn't immediately matter. it's a matter of reputation/reliability. Intel for example is trying so hard to gain their reputation back. Fabs don't compromise theor quality for any customer to keep that reputation alive. it's incredibly hard to bring something new and disruptive by a new player. you need deep pockets (10s of billions to burn) and industry insiders to somewhat buy some reputation.
only exception to this is China. it's slightly easier to do this there at the moment. through they often transfer TSMC heavy-weights to manage their fabs.
Also not a chipmaker, but my impression is silicon has tons of institutional knowledge you can’t just find online and I imagine all the upstream vendors are going to be very similar to the fabs you are trying to replace. Unlike software, hardware can’t be bootstrapped with a disruptive idea and the shirt in your back.
no. someone with decades of experience bringing silicon to market maybe, but still no one would change their supply chain for ease of use. there's nothing easy in IC design, for good reason, and the industry learned to deal with it. what the industry values the most is reliability.
if they just a had a few hundreds of billions lying around to prop up competitive fabs. absolutely!
> all the customers they could ever want
Again, the market for this is tiny. How many companies do you really think want a shuttle service?
haha, yeah, I have no desire to enter this space so I really haven't a clue. But I smell potential there; but it won't be me that takes it.
check out Musesemi. There are a bunch of companies doing this as a service.
180nm is “potato quality” but still commonly used for automotive chips like PMICs. Though I suspect you’re right that a newer node would cost the same.
180 nm fabs are getting to the point where replacing machines is prohibitively expensive and spare parts have to be custom made.
That SiFive FE-310 chip on the HiFive1 on 180nm in 2016 was a 32 bit 1 instruction per cycle 5-stage pipelined CPU running at 320 MHz.
That's way more than typical microcontrollers in embedded uses even today -- 24 or 48 MHz is very common for e.g. Cortex M0+ and you seldom find over 180 MHz for Cortex M3/M4. Those (or competitors) make up the vast bulk of the market.
That 320 MHz is with automated placement and routing with a standard cell library. Back when 180nm was new both Intel (Pentium III) and Motorola (G4) were getting 1 GHz or a bit more out of it with a lot of engineers using a much more manual process.
> 180 nm fabs are getting to the point where replacing machines is prohibitively expensive and spare parts have to be custom made.
Do you have a reference for that? I'm not sure why it would be true.
180nm lines have many other advantages, like better transistor gain for analog, lower leakage, more advanced device types and BCD. Some 180nm lines can also do MEMS. Maybe a couple of foundries are struggling but I would've thought 180nm was still going pretty strong.
180nm is still going plenty strong and the fabs get a constant stream of upgrades, but the lithography systems are officially EOL. ASML/Nikon/Canon don’t make them anymore except for the occasional (very expensive) custom order and the cost of repairing them is steadily increasing. If they don’t need the bigger node size, greenfield projects are better off with a smaller node but anyone with an existing design is going to keep using it.
It’s just a cost-curve thing - older nodes eventually hit the other end of the bathtub curve where keeping the fab running gets more and more expensive while newer nodes are still cheap.
That doesn't really match my experience. I could be totally wrong though because I don't get to look at the books.
ASML it still announcing DUV systems on their product page. I would think this would mean they would be very happy to sell you a new one. https://www.asml.com/en/products/duv-lithography-systems
And machine revitalization and refurbishment is an important selling point for this kind of capital equipment.
https://www.asml.com/en/news/stories/2023/revitalization-thr...
"Did you know that approximately 95% of ASML lithography systems sold in the past 30 years are still active in the field? As of the end of 2022, more than 5,000 of our machines are hard at work in chipmaking fabs globally – a feat made possible by the fact that our systems can be repaired, refurbished and repurposed throughout their life cycles. It’s all part of our commitment to supporting a circular economy in the semiconductor industry that reduces waste, adds value and lessens environmental impact."
"Currently there’s a growing market in the semiconductor industry for mature DUV technology solutions. Refurbished systems provide cost-effective options for chipmakers looking to scale up in that area."
Those TwinScan systems are much newer than the PAS5500 series I'm familiar with (the one they're really bragging about in that article with the 95% stat). ASML doesn't sell them anymore, they only offer the refurbishment program: https://www.asml.com/en/products/refurbished-systems
Sooner rather than later it'll be cheaper to buy a TwinScan system than to fix a PAS5500/750, but at that point why would the fab keep making 180nm chips when they can make more money making 45nm chips with the same system? Last I checked, some critical parts already had 1+ year lead times because they had to be made to order so fabs have to keep their own stock.
Edit: Sorry I misused "EOL" in a previous comment. They're still being supported my ASML, but you can't buy a new machine so expanding a fab means upgrading the node.
I suppose it depends what they're printing and why. There are plenty of structures that will want to be 180nm and larger for many years to come.
But I definitely agree that pretty soon it will make no sense to artificially limit printing resolution and, for high volume manufacturing, buying a new machine that can't do better than 180nm will make little sense.
TSMC is phasing out 180nm officially already for 2 years due to demand on more advanced nodes like 65nm or 40nm. All the BCD stuff is implemented on those processes too. They are moving the equipment used in 180nm to these newer nodes. I think they don't want anything laeger than 110nm.
Likely 180 nm is fine when you have little and slow logic, don't care about power efficiency too much, and want to integrate output pins rated at 500 mA. Much of car electronics is like this.
> 180nm is potato quality - many many generations behind. So far behind it might actually be more expensive to get chips than at 110/65nm, although I’m only speculating here.
I mean that is year 2000 level-tech. PlayStation 2/Pentium 3/AMD Duron/GameCube levels. That is not potato. You can definitely do things with it.
https://en.wikipedia.org/wiki/180_nm_process
What EDA software do you need and how much does it cost?
Normal prices are extremely high and depend on the tech node. A simple CPU development in something advanced like 5nm would probably require a license package for 30+ engineers for 2 years or so. This would cost millions of $ per year. Depends how good you negotiate your prices. Some start-ups get 99% discount if they know a guy.
The EDA is dominated by Synopsys, Cadence and Mentor Graphics. Each offer every tool but what I often see is a mix and match of tools from all three.
I suspect SiFive wouldn't be too interesting in doing that. First off, OR1K is a lot bigger than an E31. And it's only a core, not an SoC. You're probably looking at a several million dollar job for that.
Plus SiFive divested their chipmaking division, OpenFive (formerly Open-Silicon) in 2022. That would be who you'd want to talk to.
How were the 180nm chips packaged? Thanks.
It's worth noting that if you're interested in making your own custom silicon, you can get it done quite inexpensively. It's not a fast process, but if you want to try your hand at building something that is all you, you can!
This isn't want SiFive was doing - they're providing engineering expertise. Here you're allowed to put together all your own logic gates into... a thing.
https://tinytapeout.com/
TinyTapeout is cool, but the size of what you can do there is many orders of magnitude smaller than a Linux-capable OR1K core and surrounding SoC!
The typical project is more like a binary counter, or a BCD to 7-segment decoder.
I don't think you would even be able to fit a 6502 -- not the core, but also you can't have that many pins.
I think one was done with a bit-serial SeRV RV32I CPU (which is 125 LUT6 and 164 flip-flops when done in a Xilinx FPGA), but without the CPU registers fitting on the chip.
Yeah it really is for tiny chips. It is fabulous learning experience though, which is also the purpose of the project. Maybe in a few years we will have Smalltapeout where we can do microcontroller/microprocessor grade in the same way.
I took a look at your blog[0]. You aren't going to need a custom CPU. You'll be much better off with something that's already in production, in the market, well-documented and well-tested. Also it sounds like you have a pretty steep learning curve ahead of you.
[0] https://flyingcarcomputer.com/posts/a-new-personal-computer/
I’d love an actual description of how this will change personal computing. The blog post is just a bunch of small technical decisions and opinions, doesn’t mention anything about personal computing. Maybe they should build an OS variant instead? The home page blurb of “No AI. No cloud. No distractions” is already very attainable without inventing a new type of computer…
Regardless, respect. Seems daunting, but will no doubt be a really cool project.
This is one of the kindest comments I have seen here.
Optimistically tagging on here as it's a similar sort of question.
Say one lone developer gets a bit carried away with verilog and ends up with a description for a chip. I know there's an odd lot style of thing where you can get your chip drawn on a wafer along with a load of other chips from other people. There's probably a way of getting someone who knows what they're doing to attach wires to it, wrap it in plastic or whatever else is involved in "packaging".
Where does one get started with that, and what's the ballpark cost? I'm assuming a fair amount of the OP's $100k is SiFive labour, but I don't know how to guess whether a half dozen custom chips in some sort of packaging is of the order of 10s of dollars or 10s of thousands.
(edit: I've done a lot of software near hardware and have a vague idea that uploading the data to tsmc was called "tape out" and involved quite a lot of money, but I also vaguely remember talking to someone at a conference who had chips made as a hobby so there are some pieces missing from my mental model)
If you just want to put your verilog into an ASIC then it can be done fairly inexpensively these days.
For example: https://efabless.com/chipignite $10K for 100 packaged dies in QFN. Which is not totally out of hobby range (I've seen people spend way more on fixing up cars that have no business being fixed) and if you use their harness they'll solve most of the hard EE problems for you.
But you might consider why you're making the IC. If it's for the experience, sure. But if it's to make a commercial product, there's a lot more to it. For example, what's your IO solution...
Nice example, thank you. I have no interest in making a commercial product but some motivation to learn what lies below the ISA. Like you say, that's cheaper than some more common hobbies. I work in the software side of semiconductor companies so it's a reasonable spin on professional development too.
A friend recently discovered that PCBs can be ordered online for essentially zero cost and arrive in the mail and that surface mount soldering is an easy thing. Combined with a path for code to magic sand that's a whole world of dubious past times suddenly available.
Wait’ll you find out the same company that makes the PCBs will also source the parts and do the soldering for you, as well as 3D print the case — all in quantity 2 and up! All for incredibly cheap, and 6-day turnaround to your (west coast US) door. It’s a golden age for random hardware hacking. (Check out JLCPCB and PCBWay.)
You might find this course helpful then. There is a huge amount of information you need to consume to make an IC so having it all organized for you is pretty valuable. It will save you many, many, hours. :)
https://zerotoasiccourse.com
If you just want to learn how CPUs are designed then get an FPGA. The process of running a chip on an FPGA is very similar to the process of getting a custom ASIC built.
Thanks for mentioning e-fabless. When I saw $100k, the first thing I thought was "cool, now remove a zero". I love the capabilities the future is bringing.
https://tinytapeout.com/
Cool concept!
The secret is that 180nm nodes are so legacy that they have a ton of spare cycles for educational and apparently now hobbyists. Lots of various businesses are offering services now that sell the ancient 180nm node.
Overall, the plan is much like OSHPark. You build a die that can be paired up with all of the other customers for a run. If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips (before errors) and 1000 designers are happy.
*Made up numbers of course. I'm not in the business.
> If say 300 wafers are made with 1000 different designs on it, everyone gets 300ish chips
That's not how it works. The same pattern, called a "reticule" [1] is duplicated 300 times over the wafer. One wafer gives you 300 copies of whatever set of dies fit into one reticule.
[1] it's to do with the size of the optical/UV lenses that are used in mask-making
> The secret is that 180nm nodes are so legacy
That's true but they keep upping the capabilities of what the designer can do at 180nm. Based on the wait times for my jobs, there's not a lot of spare cycles, at least at the foundries I use.
180nm is declining as far as I'm aware.
Its more likely that 180nm fabs are idling so much that they've made the decision to close. There's only so low that the prices can go before these businesses don't think its worth staying in business anymore.
I've heard that over the long term, 28nm should theoretically be the "long term cost-efficient node". The 65nm and other nodes are all cheaper in practice because these factories are fully paid off by now.
It was something about 300mm wafers and overall tooling being shared with 28nm with the latest nodes + overall investments. While 200mm likely will be shutdown over the long term (but 200mm wafers will remain the cheapest solution in the short term).
So under these expectations, I'd say that 180nm, 65nm, and other old nodes will slowly shut down as everyone moves to the long-term most efficient node. Still, having the oldest nodes stay open for the educational / hobbyist / experimental R&D for some commerical companies makes sense. Especially since the wafers are smaller and thus overall runs can be smaller.